Novel Approach to FDSOI Threshold Voltage Model Validated at Cryogenic Temperatures

The paper presents a novel approach to the modeling of the back-gate dependence of the threshold voltage of Fully Depleted Silicon-On-Insulator (FDSOI) MOSFETs down to cryogenic temperatures by using slope factors with a gate coupling effect. The FDSOI technology is well-known for its capability to modulate the threshold voltage efficiently by the back-gate voltage. The proposed model analytically demonstrates the threshold voltage as a function of the back-gate voltage without the pre-defined threshold condition, and it requires only a calibration point, i.e., a threshold voltage with the corresponding back-gate voltage, front- and back-gate slope factors, and work functions of front and back gates. The model has been validated over a wide range of the back-gate voltages at room temperature and down to 3 K. It is suitable for optimizing low-power circuits at cryogenic temperatures for quantum computing applications.

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Machine Learning Based Transient Stability Emulation and Dynamic System Equivalencing of Large-Scale AC-DC Grids for Faster-Than-Real-Time Digital Twin

Modern power systems have been expanding significantly including the integration of high voltage direct current (HVDC) systems, bringing a tremendous computational challenge to transient stability simulation for dynamic security assessment (DSA). In this work, a practical method for energy control center with the machine learning (ML) based synchronous generator model (SGM) and dynamic equivalent model (DEM) is proposed to reduce the computational burden of the traditional transient stability (TS) simulation. The proposed ML-based models are deployed on the field programmable gate arrays (FPGAs) for faster-than-real-time (FTRT) digital twin hardware emulation of the real power system. The Gated Recurrent Unit (GRU) algorithm is adopted to train the SGM and DEM, where the training and testing datasets are obtained from the off-line simulation tool DSAToolsTM/TSAT®. A test system containing 15 ACTIVSg 500-bus systems interconnected by a 15-terminal DC grid is established for validating the accuracy of the proposed FTRT digital twin emulation platform. Due to the complexity of emulating large-scale AC-DC grid, multiple FPGA boards are applied, and a proper interface strategy is also proposed for data synchronization. As a result, the efficacy of the hardware emulation is demonstrated by two case studies, where an FTRT ratio of more than 684 is achieved by applying the GRU-SGM, while it reaches over 208 times for hybrid computational-ML based digital twin of AC-DC grid.

*Published in the IEEE Power & Energy Society Section within IEEE Access.

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Winners of the 2019 IEEE Access Best Multimedia Award (Part 2)

IEEE Access would like to congratulate the winners of the 2019 IEEE Access Best Multimedia Award (Part 2) and recipients of a $500 USD Amazon gift card for their fine contributions to IEEE Access. The full article entitled, “kNN-STUFF: kNN STreaming Unit for Fpgas” can be found by clicking here.

Winners of the 2019 IEEE Access Best Multimedia Award (Part 1)

IEEE Access would like to congratulate the winners of the 2019 IEEE Access Best Multimedia Award (Part 1) and recipients of a $500 USD Amazon gift card for their fine contributions to IEEE Access. The full article entitled, “Hidden Outlier Noise and its Mitigation” can be found by clicking here.

2018 IEEE Access Best Multimedia Award Part 2 Winners

IEEE Access would like to congratulate the winners of the 2018 IEEE Access Best Multimedia Award Part 2 and recipients of a $500 USD Amazon gift card for their fine contributions to IEEE Access. The full article entitled, “FPGA Acceleration for Computationally Efficient Symbol-Level Precoding in Multi-User Multi-Antenna Communication Systems” can be found by clicking here.